ExaNeSt QFDBrevA Call for Tenders

Call for Tenders
for selecting a Contractor based on Negotiations, for the:
Implementation of the "Quad-FPGA Daughter Board (revision A)" Test PCBs

Heraklion Crete Greece, 28 April 2016

FORTH invites tenders by potential contractors who can undertake the implementaiton of four (4) copies of a printed circuit board (PCB) called "QFDB revA" (Quad-FPGA Daughter Board revision A), together with four copies of an auxiliary "Feeder Board" PCB onto which the QFDB will be mounted and which will provide external interfaces (mostly SFP+) and power supplies, based on the technical specifications and design that was performed by FORTH. The budget for this implementation is up to fifty five thousand (55000) Euro, excluding VAT, and comes from FORTH's budget for the Prototype in the ExaNeSt project.

Deadline for the submission of Offers: Monday 16 May 2016, at 18:00 Greek time (17:00 CET).
Offers should be sent on paper, enclosed in two separate sealed enveloppes within one larger envelopee, each with the contents described below, to the address: FORTH - Institute of Computer Science, Nikolaou Plastira 100, Vassilika Vouton, GR-70013 Heraklion Crete GREECE.
Offers can only be made for the totality of the Goods and Services called upon.
Offers can be written in Greek or in English or in a mixture of the two.
For further information, please contact Mr. Michael Ligerakis ( ligeraki [at] ics dot forth dot gr ), telephone +302810391456.

The original of this Call, including its full details, appears at https://diavgeia.gov.gr/decision/view/70ΙΕ469ΗΚΥ-89Υ or at http://www.forth.gr/_legal/qfdb_CfTenders.pdf This is a translation into English of extensive excerpts of the Call, and especially of the technical specifications, of the terms of the Call, and of the documents that should be submitted by candidate Contractors.

Technical Specifications:

Each QFDB PCB must fully implement all the specifications and detailed schematics that have been created by FORTH and must be able to carry/accept:

four (4) IC's of type Xilinx Zynq UltraScale+ (ZU9EG) FPGA;
DRAM: four (4) DDR4 SODIMM's of 16 GBytes each, plus four (4) DDR4 chips of 2 GBytes each;
SSD storage unit connected through M.2 connector, of capacity between 480 and 960 GBytes;
other auxiliary IC's (four (4) QSPI), sockets (Samtec connector to feeder board, M.2 connector, SODIMM connectors), voltage regulators.
FORTH will provide to the contractor, under Confidentiality terms and under the terms of the final Agreement to be signed with contractor: the full electronic design that FORTH has created, full specifications, as well as the full schematics in the form of the net-list that specifies all connections between the pins of all chips and auxiliary components in OrCAD format.
It is noted that multiple high-speed serial links will be needed for proper operation, capable to operate at 16 Gbits/s each, and the design by FORTH has been created with such capacity in mind.

Concerning the system and its components, it will be necessary to ensure that:

It will comply to the analytical specifications provided by FORTH (in the form of document) for the QFDB revA PCB and the auxiliary Feeder PCB.
The electronic design will be mapped to a layout for the PCB, appropriate for fabrication, by the Contractor or its subcontractor. This PCB layout must ensure proper quality and integrity for the DDR4, LVDS, and HS (high-speed serial) signals.
The Contractor should check that the electronic design created by FORTH follows the design specifications for Xilinx UltraScale+ FPGA's that are contained in that FPGA's Reference Design by Xilinx, which the Contractor must have access to.
The Contractor has to select a Fabrication factory and an Assembly factory --possibly as its sub-contractors-- that will be able to carry out this implementation with sufficient quality; the Contractor will also have to purchase all the chips and components and give them to the assembly factory so that they be soldered onto the boards.
The Contractor will deliver the fabricated and assembled boards to FORTH for testing, and will collaborate closely and assist FORTH in testing the correct operation and quality of fabrication. Fabrication, assembly, and testing will be done in phases, as described below.
Delivery of partially populated PCB's according to the following time plan of ExaNeSt:

late May - early June 2016: layout and design check;
June 2016: four (4) Feeder and four (4) QFDB boards fabricated, but only three (3) QFDB's partially assembled with the following components: the first board with no FPGA, no SSD, no DRAM, but with all power supply and other auxiliary chips; the second board with a single FPGA and its DRAM (as well as all auxiliary chips); and the third board with two FPGA’s, their DRAM, and the SSD (as well as all auxiliary chips).
July 2016: test the assembled boards at FORTH, in close cooperation and with the assistance of the Contractor. If the test does not uncover any fatal design or manufacturing errors, then:
early August: assemble the fourth board, fully populated with all 4 of its FPGA’s and all other chips;
August 2016: test the fourth board, as above.

If one of the above tests uncovers fatal design errors under FORTH's responsibility, then the parties will put their best efforts into completing re-design and re-fabrication as fast as possible. In this case, the additional costs for the layout of the new design, procurement of new chips, and PCB re-fabrication and re-assembly will be on FORTH's side; FORTH will have the option to negotiate with the contractor or independently for these services.
FORTH will be the sole and full owner of the Intellectual Property (IP) of the design, the layout, the structure, and the boards themselves that will be manufactured according to the IP provisions of the ExaNeSt Grant and Consortium Agreements.
Ensure the collaboration and acceptance checks at all stages (test stages as well) by FORTH, and the appropriateness of the layout and HS signal integrity for the QFDB revA and Feeder PCB's.

Participation Documents - Technical Offer:

The first of the two enveloppes when submitting an Offer, marked Participation Documents - Technical Offer, must contain the following documents:

1.1 Declarations, according to Law 1599/1986, Article 8, Paragraph 4, which lists the title of this Call, and that declares that, up to the date of submission of this Offer, the candidate Contractor that submits this Offer:

Has not been convicted by an irrevesible judgement of a Court of Justice for any of the following offenses: participation to a criminal organization, bribery, fraud and money laundering, any offense related to its professional activities, or one of: misappropriation, fraud, extortion, forgery, perjury, bribery, or fraudulent bankruptcy.
Is not in a state of bankruptcy, neither in the process of declaring bankruptcy.
Is in "Good Standing" status.
Is not in a state of compulsory administration, neither in the process of being declared under compulsory administration.
Is appropriately registered under its appropriate registry service, on the date when this Call closes.
Has not been banned from public calls for tenders or otherwise legally restricted company operation.
Unequivocally accepts the terms of this Call.

1.2 Technical Offer, which should consist of:

Technical description of the Goods and Services being offered, according to the specifications of this Call.
Declaration of the Validity Time of the Offer, which has to be fourty five (45) days from the next day after this Call closes.
Declaration of the Country(ies) of Origin of the parts of the offered system/goods/services. If the candidate Contractor manufactures by itself the final product, then the offer must declare the commercial Unit where the product will be manufactured, as well as its physical location. If the candidate Contractor will not manufacture by itself the final product, then the offer must declare the commercial Unit or Units where the parts of the product may be manufactured, as well as its/their physical location(s). Also: Declaration that these commercial Units accept to provide these goods and services to the candidate Contractor, in case this Contractor is selected.
Declaration / evidence by Xilinx Inc., manufacturer of the Zynq UltraScale+ FPGAs, showing that the candidate Contractor is in a position to and has the right to provide the required samples of these chips (to FORTH), integrated/assembled onto PCBs (the QFDB boards), using means of its own or third-party services.

Fincancial Offer:

The second of the two enveloppes when submitting an Offer, marked Financial Offer, must contain information / documents such that:

The Price of the Offer can be clearly deduced from the financial Offer, which should follow the terms of this Call.
The unit price must be given in Euro.
The Financial Offer should specify separately the cost of: each FPGA chip, each SSD, each other expensive component, the cost of board manufacturing per board, the cost of board assembly per board, as well as the total cost of the system.
The Financial Offer must be signed by the candidate Contractor himself, in case that is a physical person, or by the legal representative of the legal body in case of union or consortium, or by all members of such or by their authorized representative.
The offer will be rejected if it does not clearly state the offered price or does not offer the totality of the goods and services of this Call. The offerer cannot revise or adjust the offered prices for any reason, and these will bind the offerer until complete execution of the Contract.
Any offer that contains a price adjustment term will be rejected.
The total offered price cannot exceed the budget of this Call.

Procedure for Contrator Selection and Contract Signature:

After evaluation of the offers, the selected Contrator will be invited to do the following within ten (10) days:

Sign the Contract;
Submit the Bank Guarantee for Good Execution, which must be for an amount equal to five percent (5%) of the final total negotiated price;
Submit its Certificate of Good Standing.