European Exascale System Interconnect and Storage
News / Press

Presentation of the ExaNeSt project, ETP4HPC, ESD ROUND-TABLE, 18 May 2017

ExaNeSt presentation slides by Peter Hopton (Iceotope), presented at the ESD ROUND-TABLE on "Exploiting the Potential of European HPC Stakeholders in Extreme-Scale Demonstrators" during the European HPC Summit Week at Barcelona.

Interview on ExaNeSt's exascale potential, April 2017

Martin Kersten (CWI and MonetDB Solutions) at HiPEAC CSW, April 2017 on "How ExaNeSt is clearing the memory barriers to exascale".
Interview video:

Presentation on Cooling, HPC User Forum, April 2017:

Video from the presentation:  "Cooling the EU ExaScale Project ExaNeSt", by Peter Hopton (Iceotope), presented at the HPC User Forum, Santa Fe, April 2017:

Presentation on Cooling, HPC User Forum, April 2017:

Video from the presentation:  "Cooling the EU ExaScale Project ExaNeSt", by Peter Hopton (Iceotope), presented at the HPC User Forum, Santa Fe, April 2017:

ACM SIGMOD, 26 May 2016:

Professor Martin Kersten (CWI and MonetDB Solutions), and a member of the ExaNeSt Consortium, is the recipient of the 2016 SIGMOD Systems Award for the design and implementation of MonetDB, a pioneering main-memory database system based on a columnar data organization, which is also one of the key applications in ExaNeSt.

Call for Tenders, 28 April 2016:

QFDBrevA CfT:  Call for Tenders for selecting a Contractor based on Negotiations, for the Implementation of the Quad-FPGA Daughter Board (revision A) Test PCBs.

Press Release, 7 April 2016:

ExaNoDe selects underlying technology components: The ExaNoDe project is part of a wider group of EU funded projects as part of a strategic vision for economical, low-power approaches. Together with ExaNeSt, EcoSCALE and Mont-Blanc, which are also funded from the EU framework program for research and innovation Horizon 2020, ExaNoDe will use an ARM-based architecture as a major component of its compute nodes.

Press Release, 1 February 2016:

How to fit ten million computers into a single Supercomputer? – The ExaNeSt project paves the way:  European consortium becomes the trailblazer in the development of the most challenging architectures in next-generation computing. [PDF ]

ExaNeSt in the News:

ExaNeSt in the HiPEAC 2016 Conference, Prague, Czech Republic, 18-20 January 2016

ExaNeSt kick-off meeting, 10-11 December 2015:

All ExaNeSt partners have met in Heraklion last week to get our exciting project started. During these two days of intense discussions, we exchanged on a variety of technical matters:

  • Applications for the exascale era, both in HPC and Big-data contexts
  • Interconnect architecture, implementation and simulation
  • Design of exabyte storage systems
  • Implementation of our node and rack prototypes
  • Integration and optimization of the partners' applications onto our prototypes

We also discussed many management points:

  • Project schedule and collaboration axes
  • Day-to-day management
  • Reporting of resources, publications and dissemination activities
  • Utilization of the project website and collaborative software infrastructure

A joint INFN-INAF Press Release in Reasearch Italy;  an interview about ExaNest topics in the monthly INFN newsletter;  a Press Release (in Italian) in the INFN newsletter.

Partners joined
for a family picture
in front of the
FORTH premises.

You can also view many pictures of the event on our Twitter account.

The European Exascale Projects, including ExaNeSt, were presented and discussed at a Bird-of-a-Feather session at Supercomputing'15 (SC15), in Austin, TX USA, on 19 November 2015: see the main slides here, and the overall BoF and conclusions here.

FET-HPC Projects Meeting, 30 Sep 2015:

HPC User Forum, 25 Sep. 2015:
In a video from the Disruptive Technologies session at the 2015 HPC User Forum, Peter Hopton from Iceotope presents:
ExaNeSt technology: Targeting Exascale in 2018:
Also reported in