European Exascale System Interconnect and Storage
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This Horizon2020 FET-HPC ExaNeSt project develops and prototypes solutions for some of the crucial problems on the way towards production of Exascale-level Supercomputers:

WHAT we do:

ExaNeSt develops and prototypes solutions for Interconnection Networks, Storage, and Cooling, as these have to evolve in order for the production of exascale-level supercomputers to become feasible.  We tune real HPC Applications, and we use them to evaluate our solutions.  Click for more information...

WHY we do it:

HPC is a precious tool for all of modern technology, science, and society.  For the next generation of HPC systems, we need millions of low-power-consumption computing cores, tightly interconnected and packaged together and appropriately cooled, and with a new storage architecture.  Click to see why...

HOW we do it:

We use the UNIMEM Global Address Space and zero-copy send/receive operations, and we tune our applications for such architectures. We develop efficient networking with all its frequent-path functions implemented in hardware, including advanced congestion management for full utilization at low latency; we distribute the file storage on top of that. Click to see more...

WHO we are:

The ExaNeSt Consortium combines industrial and academic research expertise, especially in the areas of system cooling and packaging, storage, interconnects, and the HPC applications that drive all of the above. Click to see who we are...

WHO we collaborate with:

The ExaNeSt consortium collaborates with two other contemporary H2020 projects: ExaNoDe (, focused on compute-node and memory concerns), and ECOSCALE (, focused on heterogeneous architectures and specifically the efficient use of FPGA-based accelerators. Click to see more...

ExaNeSt QFDB bring-up
QFDB bring-UP/testing setup
The ExaNeSt QFDB board
Liquid cooled blade concept
Thermal experiment board and heat sink
Thermal experiment boards in liquid-cooled blade
Microwave Nanophotonics Lab (UPV)
Microwave Nanophotonics Lab (UPV)
Microwave Nanophotonics Lab (UPV)
64-bit ARM Juno
512-core FPGA emulator
Interconnects Prototyping
liquid-cooling dense packaging technology
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Project Info:

Call: H2020-FETHPC-1-2014 – (a) core technologies and architectures

Project Number, CORDIS Info: 671553

Duration: 01 Dec. 2015 – 30 Nov. 2018 (36 months).

Budget: Cost: 8.44 M€, EU contribution: 8.44 M€