ExaNeSt - Publications

Generally about the Project

Overview of the Project (recent slides/poster)

ExaNeSt Summary of Results (August 2019), in 18 slides: Presentation during the EuroHPC Summit Week 2019, Poznan, Poland, 13-17 May 2019, in the 1st European Communities Workshop on Exascale Computing - Focus on High Performance Data Analytics, Thursday 16 May 2019 – update of 30 August 2019
ExaNeSt Poster at the ISC 2019 Conference, Frankfurt, Germany, 19 June 2019
ExaNeSt in 1 slide: very short summary of the project

General Papers about the Project

“Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development” Manolis Katevenis, Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose A.Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Bernd Lietzow, Angelos Mouzakitis, Nikolaos Chrysos, Manolis Marazakis, Paolo Gorlani, Stefano Cozzini, Giuseppe Piero Brandino, Panagiotis Koutsourakis, Joeri van Ruth, Ying Zhang, Martin Kersten. Microprocessors and Microsystems, Vol 61, pp. 58 - 71, September 2018, DOI: [10.1016/j.micpro.2018.05.009]
"The next Generation of Exascale-class Systems: the ExaNeSt Project", by R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, John Goodacre, Mikel Lujan, J. Navaridas, J. P. Saiz, N. Chrysos, and M. Katevenis for the ExaNeSt team. Euromicro Conference on Digital System Design (DSD), pp. 510–515, August 2017. DOI: [10.1109/DSD.2017.20]
"Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project", by R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Pisani, F. Simula, P. Vicini, J. Navaridas, F. Chaix, N. Chrysos, M. Katevenis, V. Papaefstathiou, Journal of Physics: Conference Series, vol. 898, no. 8, p. 082045, November 2017. DOI: [10.1088/1742-6596/898/8/082045]
“The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems”, by M. Katevenis, N. Chrysos, M. Marazakis, I. Mavroidis, F. Chaix, N. Kallimanis, J. Navaridas, J. Goodacre, P. Vicini, A. Biagioni, P. S. Paolucci, A. Lonardo, E. Pastorelli, F. Lo Cicero, R. Ammendola, P. Hopton, P. Coates, G. Taffoni, S. Cozzini, M. Kersten, Y. Zhang, J. Sahuquillo, S. Lechago, C. Pinto, B. Lietzow, D. Everett, and G. Perna. : Euromicro Conference on Digital System Design (DSD), pp. 60–67, August 2016, DOI: [10.1109/DSD.2016.106]

Overview (older)

Presentation of the ExaNeSt project at the "ARM: On the Road to HPC" (hosted by the Mont-Blanc Project); UPC, Barcelona, Spain - January 16-17, 2017.
ExaNeSt as of May 2016, in 8 slides: Presentation of the ExaNeSt project at the European HPC Summit Week 2016; Prague, Czech Republic, 10 May 2016. DOI: [10.5281/zenodo.802223]
ExaNeSt Poster at the HiPEAC 2017 Conference, Stockholm, Sweden, 25 January 2017. DOI: [10.5281/zenodo.802211]
ExaNeSt Poster at the HiPEAC 2016 Conference, Prague, Czech Republic, 20 January 2016. DOI: [10.5281/zenodo.802215]
(Older): ExaNeSt in 5 minutes and in 6 slides: Presentation of the ExaNeSt project at the first meeting of the FET-HPC projects that resulted from the November 2014 Call; Rome, 30 September 2015.

Interconnects

“Enabling Standalone FPGA Computing”, by Joshua Lant, Javier Navaridas, Andrew Attwood, Mikel Lujan and John Goodacre. IEEE Symposium on High Performance Interconnects (HOTI’19). Santa Clara, CA, USA, August 14th-16th, 2019.
"Design Exploration of Multi-tier interconnects for Exascale systems", by J Navaridas, J Lant, JA Pascual, M. Luján, J Goodacre. International Conference on Parallel Processing (ICPP’19). Kyoto, Japan, August 2019.
"INRFlow: An interconnection networks research flow level simulation framework" by Javier Navaridas, Jose A. Pascual, Alejandro Erickson, Iain A. Stewart, Mikel Lujan. Journal of Parallel and Distributed Computing, vol. 130, pp. 140 - 152, August 2019, DOI: [10.1016/j.jpdc.2019.03.013]
“Software and Hardware co-design for low-power HPC platforms”, Manolis Ploumidis, Nikolaos D. Kallimanis, Marios Asiminakis, Nikos Chrysos, Pantelis Xirouchakis, Michalis Gianoudis, Leandros Tzanakis, Nikolaos Dimou, Antonis Psistakis, Panagiotis Peristerakis, Giorgos Kalokairinos, Vassilis Papaefstathiou, and Manolis Katevenis,, Exacomm, collocated with ISC, Frankfurt, Germany, June 20, 2019
"Receive-side notification for enhanced RDMA in FPGA-based networks", by J Lant, A Attwood, J Navaridas, M Lujan and J Goodacre. 32nd International Conference on Architecture of Computing Systems (ARCS’19), Copenhagen, May 2019. DOI: [10.1007/978-3-030-18656-2_17]
“Direct Communication between Distributed FPGA Resources”, by J. Lant, J. Navaridas . Emit, Huddersfield, UK, April 2019.
“Scalability of a Silicon Photonic Switch for High-Performance Interconnects”, by M. Kynigos, J. Navaridas and J. A. Pascual. Emit, Huddersfield, UK, April 2019.
"Dynamic Max-Min Fair Rate Regulation Apparatuses, Methods, and Systems": US Patent Number US10158574B2 (18 Dec. 2018), European Patent Number 3198810 (18 Feb. 2019); by Manolis Katevenis, FORTH (work started in the EuroServer project, then continued in the ExaNeSt project).
“Accurate congestion control for RDMA transfers”, by D. Giannopoulos, N. Chrysos, E. Mageiropoulos, G. Vardas, L. Tzanakis, and M. Katevenis: , Proc. of the 12th ACM/IEEE Int. Symposium on Networks-on-Chips (NOCS 2018), Turin, Italy, 4-5 Oct. 2018, pp. 1-8; DOI: [10.1109/NOCS.2018.8512155]
"I/O, today, is Remote (block) Load/Store, and must not be slower than Compute, any more": Invited Talk, given by Manolis Katevenis, at the PER-18 Workshop (PERspectives on the Future of Computing), within the HiPEAC Computing Systems Week (CSW), Goteborg (Gothenburg), Sweden, 23 May 2018; video of the talk available.
“Virtualized Multi-Channel RDMA with Software-Defined Scheduling”, by Kyriakos Paraskevas, Nikolaos Chrysos, Vassilis Papaefstathiou, Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Giannioudis, Manolis Katevenis, Vol 136, pp. 82 - 90, 2018, DOI: [10.1016/j.procs.2018.08.240]
"Enabling Shared Memory Communication in Networks of MPSoCs", by J Lant, C Concatto, A Attwood, J Pascual, M Ashworth, J Navaridas, M Luján, and A Goodacre. Concurrency and Computation: Practice and Experience. September 2018. DOI: [10.1002/cpe.4774]
"High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings", by JA Pascual and J Navaridas. Intl. Conf. on Supercomputing (ICS '18),pp. 129-138, Beijing, China, June 2018,. DOI: [10.1109/HOTI.2017.18]
“Network-on-chip evaluation for a novel neural architecture”, by M Kynigos, J Navaridas, LA Plana, and S Furber. 15th ACM International Conference on Computing Frontiers (CF '18), Ischia, Italy, May 2018.. DOI: [10.1145/3203217.3203268].
"A CAM-free Exascalable HPC Router", by C Concatto, JA Pascual, J Navaridas, J Lant, A Attwood, M Lujan and J Goodacre. 31st International Conference on Architecture of Computing Systems, ARCS’18, Braunschweig, Germany, 9th-12th April 2018. DOI: [10.1007/978-3-319-77610-1_8]
"Multi-tier Interconnect and Mechanisms for Exascale Communication", by J. Navaridas, P. Viciny, e.a. Presentation at the Workshop "ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects", in conjunction with the HiPEAC 2018 Conference, Manchester, UK, 23 January 2018.
"Large scale low power computing system: Status of network design in ExaNeSt and EuroEXA projects", by R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontisso, F. Simula, and P. Vicini. Advances in Parallel Computing, vol. 32, pp. 750–759, 2018. DOI: [10.3233/978-1-61499-843-3-750]
"High signal-to-noise ratio ultra-compact lab-on-a-chip microflow cytometer enabled by silicon optical antennas", by Sergio Lechago, Carlos García-Meca, Amadeu Griol, Nuria S. Losilla and Javier Martí. Opt. Express, 26, 25645–25656 (2018). (JOURNAL EDITOR’S PICK), DOI: [10.1364/OE.26.025645]
"A Survey on Optical Network-on-Chip Architectures", by S Werner, J Navaridas, and M Luján. ACM Computing Surveys, 50(6), January 2018. DOI: [10.1145/3131346]
"Cluster Communication Latency: towards approaching its Minimum Hardware Limits, on Low-Power Platforms": Invited Talk, given by Manolis Katevenis, at the Stamatis Vassiliadis 2017 Symposium, held in conjunction with the IEEE SAMOS XVII Conference, Samos Island, Greece, 19 July 2017.
"Low Latency RDMA for High-Performance Computing on ARM Platforms", Fiuggi, Italy: HiPEAC ACACES 2017 Poster presentation by Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Gianoudis, Antonis Psistakis, Giorgos Kalokerinos, Nikos Chrysos, Vassilis Papaefstathiou, Manolis G.H. Katevenis, FORTH July 10-14 2017
"Subchannel Scheduling for Shared Optical On-chip Buses", by S. Werner, J. Navaridas and M. Luján. 25th Annual IEEE Symposium on High-Performance Interconnects (HOTI), Santa Clara, CA, August 28-30, 2017, pp. 49-56. DOI: [10.1109/HOTI.2017.18]
"Designing Low-power, Low-latency Networks-on-Chip by Optimally Combining Electrical and Optical Links", by S Werner, J Navaridas, M Luján. International Symposium on High-Performance Computer Architecture (HPCA-23), Austin, TX, USA, February 2017. Received a HiPEAC Award, DOI: [10.1109/HPCA.2017.23]
"Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip", by S Werner, J Navaridas, and M Luján. Journal of Optical Communications and Networking, 9(5), pp. 364-374, 2017. DOI: [10.1364/JOCN.9.000364]
"Designing an Exascale Interconnect using Multi-objective Optimization", by Jose A. Pascual, Joshua Lant, Andrew Attwood, Carol Concatto, Javier Navaridas, Mikel Lujan and John Goodacre. IEEE Congress on Evolutionary Computation, San Sebastian, Spain, June 2017. DOI: [10.1109/CEC.2017.7969572]
"On-chip wireless silicon photonics: from reconfigurable interconnects to lab-on-chip devices", by Carlos García-Meca, Sergio Lechago, Antoine Brimont, Amadeu Griol, Sara Mas, Luis Sánchez, Laurent Bellieres, Nuria S Losilla & Javier Martí. Nature: Light Science & Applications, (2017)6, e17053, September 2017, DOI: [10.1038/lsa.2017.53]
“Modeling a Photonic Network for Exascale Computing”, by Jose Duro, Salvador Petit, Julio Sahuquillo and Maria E. Gomez. 3rd International Workshop on Modeling and Simulation of Parallel and Distributed Systems (MSPDS 2017), Genoa, Italy, July 17th 21st, 2017 (to appear). DOI: [10.5281/zenodo.823624]
"Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework", by Jose Puche, Sergio Lechago, Salvador Petit, María E. Gómez and Julio Sahuquillo. Workshop on Modeling and Simulation of Parallel and Distributed Systems (held in conjunction with the High Performance Computing & Simulation (HPCS) conference), Innsbruck, Austria, July 2016. DOI: [10.5281/zenodo.804004
"Challenges and Opportunities in Exascale-Computing Interconnects": Keynote Talk, given by Manolis Katevenis and Nikolaos Chrysos, at the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS 2016), held in conjunction with the HiPEAC 2016 Conference, Prague, Czech Republic, 18 January 2016. DOI: [10.5281/zenodo.802230]

Virtualization

"Lightweight and Generic RDMA Engine Para-virtualization for the KVM Hypervisor", by Angelos Mouzakitis, Christian Pinto, Nikolay Nikolaev, Alvise Rigo, Daniel Raho, Babis Aronis, Manolis Marazakis. International Conference on High Performance Computing & Simulation (HPCS 2017), Genoa, Italy, July 2017. DOI: [10.5281/zenodo.807607]

Storage & Data Access

"An Efficient Memory-Mapped Key-Value Store for Flash Storage", by Anastasios Papagiannis, Giorgos Saloustros, Pilar González-Férez, Angelos Bilas. Appears in: Proceedings of SoCC ’18: ACM Symposium on Cloud Computing (SoCC ’18), Carlsbad, CA, USA, October 11–13, 2018. DOI: [10.1145/3267809.3267824]
"On the Effects of Allocation Strategies for Exascale Computing Systems with Distributed Storage and Unified Interconnects", by Pascual Saiz, J, Lant, J, Concatto, C, Attwood, A, Navaridas, J, Luján, M and Goodacre, A 2018, Concurrency and Computation: Practice and Experience, DOI: [10.1002/cpe.4784]
“On the Effects of Data-aware Allocation on Fully Distributed Storage Systems for Exascale”, by JA Pascual, C Concatto, J Lant, and J Navaridas. ROME Workshop (in conjunction with Europar 2017),), Santiago de Compostela, Spain, August - September 2017. DOI: [10.1007/978-3-319-75178-8_58]
"Implementation Notes for the Storage and Data Access Infrastructure", ExaNeSt project Deliverable D4.3, 30 May 2017 (version 1.0). DOI: [10.5281/zenodo.802198]
“Iris: An optimized I/O stack for low-latency storage devices”, by Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis and Angelos Bilas. ACM SIGOPS Operating Systems Review - Special Topics, Volume 50, Issue 3, December 2016, Pages 3-11, DOI: [10.1145/3041710.3041713]
"User-space I/O for μs-level storage devices", by Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis and Angelos Bilas. Appears in: Michela Taufer, Bernd Mohr, Julian M. Kunkel (Eds.): High Performance Computing, LNCS 9945, ISC High Performance 2016 International Workshops ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P3MA, VHPC, WOPSSS Frankfurt, Germany, June 19–23, 2016, Revised Selected Papers. DOI: [10.1007/978-46079-6_44]. Extended version appeared in ACM SIGOPS Operating Systems Review - Special Topics, Volume 50, Issue 3, December 2016, Pages 3-11. DOI: [10.1145/3041710.3041713]
"Distributed Processing and Transaction Replication in MonetDB - Towards a Scalable Analytical Database System in the Cloud", by Ying Zhang, Dimitar Nedev, Panagiotis Koutsourakis, and Martin Kersten. Final Public Workshop from LeanBigData and CoherentPaaS (in conjunction with the DISCOTEC16 conference), 2016. DOI: [10.5281/zenodo.803988]

Technology

"Compact Packaging and Liquid Cooling Technology for Exascale", by P. Hopton, F. Chaix, A. Ioannou, N. Kossifidis, M. Ligerakis, I. Mavroidis, M. Katevenis. Presentation at the Workshop "ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects", in conjunction with the HiPEAC 2018 Conference, Manchester, UK, 23 January 2018.
Presentation "Cooling the EU ExaScale Project ExaNeSt", by Peter Hopton, HPC User Forum, Santa Fe, April 2017.

Applications

I. Vardas, M. Ploumidis and M. Marazakis, "Towards Communication Profile, Topology and Node Failure Aware Process Placement", 2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Porto, Portugal, 2020, pp. 241-248, DOI: [10.1109/SBAC-PAD49847.2020.00041]
"Direct N-body code on low-power embedded ARM GPUs", by D. Goz, S. Bertocco, L. Tornatore, G. Taffoni, Computing Conference, London, 2019, in press, DOI: [10.1007/978-3-030-22871-2_14]
"Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems", by, F. Simula, E. Pastorelli, P. S. Paolucci, M. Martinelli, A. Lonardo, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, L. Pontisso, P. Vicini, R. Ammendola, 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 283-290, Pavia, Italy, 2019. DOI: [10.1109/EMPDP.2019.8671627]
"Exploiting the ExaNeSt Communication Primitives for a High Performance MPI Library", by M. Ploumidis, A. Psistakis, M. Asiminakis, P. Xirouchakis, M. Gianioudis, P. Peristerakis, F. Chaix, V. Papaefstathiou, N. Chrysos, M. Katevenis. Presentation at the Workshop "ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects", in conjunction with the HiPEAC 2018 Conference, Manchester, UK, 23 January 2018.
"Re-Engineering Astrophysical and Material Science Codes", by L. Tornatore, G. Taffoni, D. Goz, P. Gorlani, G.P. Brandino, S. Cozzini, L. Lavagno. Presentation at the Workshop "ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects", in conjunction with the HiPEAC 2018 Conference, Manchester, UK, 23 January 2018.
"The brain on low power architectures: Efficient simulation of cortical slow waves and asynchronous states", by R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontisso, F. Simula, and P. Vicini, Advances in Parallel Computing, vol. 32, pp. 760–769, 2018. DOI: [10.3233/978-1-61499-843-3-760]
"Gaussian and Exponential Lateral Connectivity on Distributed Spiking Network Simulation", by E. Pastorelli, P. S. Paolucci, F. Simula, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, L. Pontisso, P. Vicini, R. Ammendola. 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), pp. 658-665, Cambridge, United Kingdom, 2018. DOI: [10.1109/PDP2018.2018.00110]
“Enabling Standalone FPGA Computing” by Joshua Lant, Javier Navaridas, Andrew Attwood, Mikel Lujan and John Goodacre. IEEE Micro, invited paper.
"ExaNeSt poster on eXact-lab activities" within the project mainly openCL miniMD port on FPGA, presented at the 33rd International CAE Conference by eXact Lab, Vicenza, Italy, 6 Nov - 7 Nov 2017
"Requirement analysis (Network and Storage) and porting roadmap", ExaNeSt project Deliverable D2.2, 28 November 2016 (version 1.1 of 12 January 2017). DOI: [10.5281/zenodo.802185]
"Census of the Applications", ExaNeSt project Deliverable D2.1, 29 February 2016 (version 1.2 of 16 June 2016). DOI: [10.5281/zenodo.802165]

Others

"Preliminary Dissemination Report", ExaNeSt project Deliverable D7.1, 20 January 2017 (version 1.0). DOI: [10.5281/zenodo.802203]