ExaNeSt - News / Press

ExaNeSt in the News, 24 Sept 2019

THE NEXT PLATFORM: "Europeans Push FPGA-Powered Exascale Prototype Out the Door"

ExaNeSt Project Successfully Builds Prototype for Exascale, 16 September 2019

12 Blade HPC Testbed of ExaNeSt in Liquid-Cooling Rack

Today the whole world is trying to push supercomputer technology to the exascale level, i.e. a billion billion calculations per second. In Europe, this exascale vision will be made possible with contributions by Consortia funded by the Horizon 2020 Programme of the EU in projects such as ExaNeSt, which built a first ‘straw man’ prototype, having worked on this since 2016.

The ExaNeSt Consortium consists of twelve partners across seven EU countries, each of them with expertise in a core technology needed for innovation to reach exascale. ExaNeSt has taken a sensible integrated approach to co-design the hardware and software that is needed to enable the prototype to run in real-life evaluations.

The prototype is now successfully built, demonstrating energy efficiency in a High-Performance Computing (HPC) testbed: the energy consumed for solving a given problem on this new platform is 3 to 10 times lower than what traditional HPC processors of the same time generation consume for solving the same problem. The substantial prototype has been validated through the execution of full HPC applications from materials science, climate forecasting, computational fluid dynamics, astrophysics, neuroscience, and a database.

ExaNeSt addressed key issues such as energy efficiency by using ARM cores, moving data across shorter distances, and avoiding unneeded copyings of data; it uses power-efficient and silent liquid cooling; the prototype has non-volatile memories integrated into the processor fabric and innovative fast interconnects, while we worked to avoid congestion.

ExaNeSt has contributed to a new generation of European Supercomputers, thus creating new business opportunities. The project’s advances in performance and efficiency will enable SME's in several sectors of the economy to utilize HPC and data analytics, with an attractive trade-off between usability and affordability. ExaNeSt has also educated numerous young engineers, contributing to close the large skills gap in academia and industry.

The energy-efficient solutions are expected to spread to standard off the shelf computing systems, assisting the efforts of the EU to reduce carbon dioxide emissions and reach environmental targets.

ExaNeSt collaborates with other European R&D projects and partners, including:

EuroServer, which developed the underlying efficient communication between ARM processors;
ExaNoDe, which focused on novel three-dimensional integration technologies and on systems software;
ECOSCALE, which develops programmable-hardware accelerators for specialized computations;
EuroEXA, which is the follow-on project of the above;
Kaleao Ltd., which enables and produces new generation computing platforms by converging compute, storage, and networking into efficient, extremely compact, and transparent server solutions.
Xilinx Inc., providing FPGA technology and flexible high speed communication.
Micron Inc., for advanced low power memory and storage technology.

PRESS RELEASE in PDF: ExaNeSt Project Successfully Builds Prototype for Exascale

VIDEO on Youtube: https://www.youtube.com/watch?v=oEBJiP0wmPQ

ExaNeSt in the News :

insideHPC: https://insidehpc.com/2019/09/exanest-project-successfully-builds-prototype-for-exascale

Primeur Magazine: http://primeurmagazine.com/weekly/AE-PR-10-19-88.html

ExaNeSt Milestone-4 achieved: Six-Blade HPC Testbed up and running, 16 April 2019

The HPC Testbed Prototype that ExaNeSt is building has now been upgraded, it is up and running 24/7, and it is being used by the partners of the project for running our Applications on it and evaluating the System as well as the effects of the tuning of the Applications during the project.

This HPC Testbed consists now of 6 liquid-cooled Blades, which contain a total of 24 "QFDB" daughter boards.

This amounts to a total of 96 nodes (FPGAs) in the system, containing in total: 384 processor cores (64-bit A53's), 1.5 TeraBytes of DRAM memory, and 6 TeraBytes of Solid-State Disk (SSD) storage.

The Interconnection Topology is a 3-Dimensional Torus using the project's own switches and routing functions, and the network interfaces feature ExaNeSt-own remote DMA engines with 1024 channels each, multiple mailbox queues, and resilience features.

The intra-QFDB links transfer 16 Gigabits per second each, at a sub-microsecond latency.

Our MPI library now contains multiple features for high performance, and the BeeGFS parallel file system has been integrated.

Boot reliability and speed have been improved, and the management network uses 10 GigEthernet.

Overall operational reliability is improved, including the handling of page faults during RDMA operations and network timeouts and retransmissions in hardware and using coprocessors.

This HPC Testbed has now been in continuous operation for many days, successfully running multiple Applications, including the very demanding HPCG Benchmark on all 384 cores for many hours.

More Blades will be added next month.